The present invention relates to a semiconductor memory device, and more particularly, to a technique for reducing current consumption of a semiconductor memory device by controlling toggling of a clock.
FIG. 1 is a block diagram illustrating a DQ peripheral circuit and a clock tree in a conventional double data rate version 3 (DDR3) semiconductor memory device.
In general, the semiconductor memory device includes an AC peripheral circuit, and a DQ peripheral circuit. The AC peripheral circuit includes pads for receiving an address, a command and a clock, a clock buffer, and a command decoder. The DQ peripheral circuit refers to a region where data input/output pads and circuits for controlling the pads are gathered.
A delay locked loop (DLL) 110 of the AC peripheral circuit is used to compensate a skew between an external clock and an internal clock in the semiconductor memory device. The DQ peripheral circuit controls data output using rising and falling clocks RCLKDLL and FCLKDLL output from the DLL 110.
The rising clock RCLKDLL and the falling clock FCLKDLL output from the DLL 110 have a 180-degree phase difference. Rising and falling clocks RCLKDLL and FCLKDLL having a 180-degree phase difference are used because if a duty cycle changes during clock transfer in the case where just one clock is transferred to the DQ peripheral circuit, operation timing of a control circuit using a falling edge of the clock becomes mismatched.
The DQ peripheral circuit includes a domain crossing unit 120 and a clock transfer unit 130.
The clock transfer unit 130 transfers the rising clock RCLKDLL and the falling clock FCLKDLL output from the DLL 110 to a first buffer unit 140 and a second buffer unit 150. The semiconductor memory device may operate in an x8 mode or an x16 mode according to the number of data input/output pins (DQ pin) being used. In the x8 mode, the clock transfer unit 130 transfers the rising clock RCLKDLL and the falling clock FCLKDLL only to the first buffer unit 140. This is because data is output using only eight data pins. In the x16 mode, the clock transfer unit 130 transfers the rising clock RCLKDLL and the falling clock FCLKDLL to the first buffer unit 140 and the second buffer unit 150. It should be noted that although the clocks are distinguished by letters L and U in order to distinguish clocks being transferred to the first buffer unit 140 from clocks being transferred to the second buffer unit 150, but those clocks are fundamentally identical to each other.
The first buffer unit 140 supplies a rising clock RCLKDLL and a falling clock FCLKDLL to data output units 161 to 168, and the second buffer unit 150 supplies a rising clock RCLKDLL and a falling clock FCLKDLL to data output units 169 to 176. Then, the data output units 161 to 176 align data at the rising clock RCLKDLL and the falling clock FCLKDLL to output data to the outside of the semiconductor memory device. The data output units 161 to 176 refer to a circuit for controlling data output, such as a pipe latch that aligns and outputs data such that the data can be output to the data pin (DQ pin).
The domain crossing unit 120 is a circuit that generates an internal read command LATENCY synchronized with an internal clock RCLKDLL in response to a read command RDCMD input in synchronization with an external clock CLK. This is because in a read operation of the semiconductor memory device, the operation must be performed with reference to the internal clock RCLKDLL or FCLKDLL, which is an output clock of the DDL 110.
FIG. 2 is block diagram illustrating internal blocks of the domain crossing unit 120 of FIG. 1.
The domain crossing unit 120 includes a DLL counter 240, an EXT counter 260, a comparator 270, an initializer 220, a D flip-flop 210, a latch 250, and a replica 230.
An OERST signal OERST is a signal that enables the domain crossing unit 120. The initializer 220 is a circuit that determines an initial value of the DLL counter 240 according to a CAS latency CL<5:11> set in a mode resistor set (MRS). DDR3 supports CL5 to CL11. The replica 230 is a delay circuit based on skew-modeling between an external clock CLK and an internal clock RCLKDLL of the semiconductor memory device. Thus, the replica 230 has a delay value equal to the skew between the external clock CLK and the internal clock RCLKDLL.
The domain crossing will now be described. When the OERST signal OERST, i.e., an enable signal, is enabled, the D flip-flop 210 latches the OERST signal OERST in synchronization with a falling edge of the internal clock RCLKDLL. Then, a DLLRST signal DLLRST output as a result of the latching of the OERST signal OERST by the D flip-flip 210 enables the initializer 220. The initializer 220 enables the DLL counter 240. The DLL counter 240 increases a DLL counter code value DLLCNT<2:0> from an initial value set by the initializer 220 whenever the internal clock RCLKDLL is enabled. The DLLRST signal DLLRST is delayed by the skew between the external clock CLK and the internal clock RCLKDLL while passing through replica 230, and latched to the latch (D-LATCH) 250. An EXRST signal EXRST latched by the latch 250 enables the EXT counter 260. The EXT counter 260 increases an EXT counter code value EXTCNT<2:0> whenever the external clock CLK is enabled. Unlike the DLL counter 240, the EXT counter 260 has an initial value of zero.
The comparator 270 stores the EXT counter code value EXTCNT<2:0> of the EXT counter 260 at the moment when a read command RDCMD is enabled. The comparator 270 enables an internal read command LATENCY at the moment when the DLL counter code value DLLCNT<2:0> becomes equal to the stored EXT counter code value EXTCNT<2:0>.
FIG. 3 is a timing diagram illustrating the operation of the domain crossing unit 120.
Specifically, FIG. 3 illustrates domain crossing in the case of CL=6. If the internal read command LATENCY must be generated at CL-3, which means the time after three clock periods elapse from the input of an external read command RD because CL=6, that is, if the internal read command LATENCY is enabled three clock periods before data output and thus the data output must be prepared, an initial value of the DLL counter code value DLLCNT<2:0> is set to five. The DLLRST signal DLLRST and the EXTRST signal EXTRST signal are enabled with a time difference as long as a skew (tDLL) between an external clock and an internal clock. Then the DLL counter code value DLLCNT<2:0> is counted from the initial value five, and the EXT counter code value EXTCNT<2:0> is counted from the initial value, zero.
When the read command RDCMD is applied in this state, the EXT code value EXTCNT<2:0> is stored in response to the read command RDCMD, e.g., “two” is stored in the case of FIG. 3. The internal read command LATENCY is enabled at the moment when the DLL counter code value DLLCNT<2:0> becomes equal to the stored EXT code value EXTCNT<2:0>, which is two.
In FIG. 3, the internal read command LATENCY is enabled at the point CL-3. This means that the DQ peripheral circuit begins preparation for data output three clock periods before the actual data output.
Meanwhile, in semiconductor memory devices, operating frequencies increase as operation speeds gets higher from DDR2 to DDR3, and current consumption also increases because of clock toggling at a higher rate. Referring to FIG. 1 the rising and falling clocks RCLKDLL and FCLKDLL output from the DLL 110 are transferred to the first clock buffer unit 140 and the second clock buffer unit 150 through the clock transfer unit 130 and then are transferred to each of the data output units 161 to 176. Accordingly, all the blocks illustrated in the DQ peripheral circuit of FIG. 1 continuously consume current because of continuous toggling of the rising and falling clocks RCLKDLL and FCLKDLL.